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rev b 33 mhz/32-bit pci target with embedded programmable logic and dual port sram ql5130 - quickpci tm last updated 12/1099 device highlights high performance pci controller n 32-bit / 33 mhz pci target n zero-wait state pci target provides 132 mb/s transfer rates n programmable back-end interface to optional local processor n independent pci bus (33 mhz) and local bus (up to 160 mhz) clocks n fully customizable pci configuration space n configurable fifos with depths up to 128 n reference design with driver code (win 95/98/win 2000/ nt4.0) available n pci v2.2 compliant n supports type 0 configuration cycles n 3.3v, 5v tolerant pci signaling supports universal pci adapter designs n 3.3v cmos in 144-pin tqfp, 208-pin pqfp and 256-pbga n supports endian conversions n unlimited/continuous burst transfers supported extendable pci functionality n support for configuration space from 0x40 to 0x3ff n multi-function, expanded capabilities, & expansion rom capable n power management, compact pci, hot-swap/hot-plug compatible n pci v2.2 power management spec compatible n pci v2.2 vital product data (vpd) configuration support n programmable interrupt generator n i 2 o support with local processor n mailbox register support programmable logic n 57k system gates / 619 logic cells n 13,824 ram bits, up to 157 i/o pins n 250 mhz 16-bit counters, 275 mhz datapaths, 160 mhz fifos n all back-end interface and glue-logic can be implemented on chip n 6 64-deep fifos (2 rams each) or 3 128-deep fifos (4 rams each) or a combination that requires 12 or less quicklogic ram modules n (2) 32-bit busses interface between the pci controller and the programmable logic figure 1. ql5130 diagram architecture overview the ql5130 device in the quicklogic quickpci esp (embedded standard product) family provides a com- plete and customizable pci interface solution com- bined with 57,000 system gates of programmable logic. this device eliminates any need for the designer to worry about pci bus compliance, yet allows for the maximum 32-bit pci bus bandwidth (132 mb/s). the programmable logic portion of the device con- tains 619 quicklogic logic cells, and 12 quicklogic dual-port ram blocks. these configurable ram blocks can be configured in many width/depth combi- nations. they can also be combined with logic cells to form fifos, or be initialized via serial eeprom on power-up and used as roms. see the ram section of this data sheet for more information. the ql5130 device meets pci 2.2 electrical and tim- ing specifications and has been fully hardware-tested. this device also supports the win'98 and pc'98 stan- dards. the ql5130 device features 3.3-volt opera- tion with multi-volt compatible i/os. thus it can easily operate in 3.3-volt systems and is fully compati- ble with 3.3v, 5v and universal pci card develop- ment. &rqilj 6sdfh +ljk 6shhg /rjlf &hoov . *dwhv 0+] ),)2v 7$5*(7 &21752//(5 +,*+ 63((' '$7$ 3$7+ ,17(5)$&( 352*5$00$%/(/2*,& 3&, %xv 0+] elwv gdwd dqg dgguhvv 8vhu ,2 3&, &21752//(5 d evice h ighlights a rchitecture o verview
2 rev b ql5130 - quickpci tm pci interface the pci target is pci 2.2 compliant and supports 32-bit/33 mhz operation. it is capable of zero wait- state infinite-length read and write transactions (132 mbytes/second). transaction control is available via the user interface as retries, wait-states, or premature transaction termination may be induced if necessary. the pci configuration registers are implemented in the programmable region of the device, leaving the designer with ample flexibility to support optional features. the ql5130 device supports maximum 32-bit pci transfer rates, so many applications exist which are ideally suited to the device's high performance. high-speed data communications, telecommunica- tions, and computing systems are just a few of the broad range of applications areas that can benefit from the high speed pci interface and programmable logic. pci configuration space the ql5130 supports customization of required configuration registers such as vendor id, device id, subsystem vendor id, etc.. quicklogic provides a reference configuration space design block. since the pci configuration registers are imple- mented in the programmable region of the ql5130, the designer can implement optional features such as multiple 32-bit base address registers (bars) and multiple functions, as well as support the following pci commands: i/o read, i/o write, memory read, memory write, config read (required), configuration write (required), memory read multiple, memory read line, and memory write and invalidate. addi- tionally, the device supports extended capabilities registers, expansion roms, power management, compactpci hot-plug/hot-swap, vital product data, i 2 0, and mailbox registers. pci address and command decoding is performed by logic in the programmable section of the device. this allows support for any size of memory or i/o space for back-end logic. it also allows the user to imple- ment any subset of the pci commands supported by the ql5130. quicklogic provides a reference address register/counter and command decode block. architecture overview the ram modules in the programmable region can be used to create configurable 32-bit fifos. each 32-bit fifo can be independently assigned to target address space for read pre-fetch or write posting. using the 12 quicklogic ram modules, the combi- nations include: ? 6 independent 64-deep fifo (2 rams each), or ? 3 independent 128-deep fifos (4 rams each), or ? a combination of the above that requires 12 or less quicklogic ram modules asynchronous fifos (with independent read and write clocks) are also supported. figure 2. graphical interface to create fifo pci i nterface a ddress and c ommand d ecode pci c onfiguration s pace a rchitecture o verview
rev b 3 ql5130 - quickpci tm internal pci interface figure 3. pci interface symbol the symbol used to connect to the pci interface of the ql5130 is shown below. this symbol is used in schematic or mixed schematic/hdl design flows in the quick works software. internal pci interface
4 rev b ql5130 - quickpci tm internal interface signal descriptions signals used to connect to the pci interface in the ql5130 are described below. the direction of the signal indi- cates if it is an input provided by the local interface (i) or an output provided by the pci interface (o). usr_addr_wrdata[31:0] o target address, and data from target writes. during all target accesses, the address will be presented on usr_addr_wrdata[31:0] and simultaneously, usr_adr_valid will be active. during target write transactions, this port will also present write data to the pci configuration space or user logic. usr_cbe[3:0] o pci command and byte enables. during target accesses, the pci command will be presented on usr_cbe[3:0] and simultaneously, usr_adr_valid will be active. during target read or write transactions, this port will present active-low byte-enables to the pci configuration space or user logic. usr_adr_valid o indicates the beginning of a pci transaction, and that a target address is valid on usr_addr_wrdata[31:0] and the pci command is valid on usr_cbe[3:0]. when this signal is active, the target address must be latched and decoded to determine if this address belongs to the devices memory space. also, the pci command must be decoded to determine the type of pci transaction. on subsequent clocks of a target access, this signal will be low, indicating that an address is not present on usr_addr_wrdata[31:0]. usr_adr_inc o indicates that the target address should be incremented, because the previous data transfer has completed. during burst target accesses, the target address is only presented to the back-end logic at the beginning of the transaction (when usr_adr_valid is active), and must therefore be latched and incremented (by 4) for subsequent data transfers. note that during write transactions, usr_adr_inc indicates valid data on usr_addr_wrdata[31:0] that must be accepted by the back-end logic (regardless of the state of usr_rdy). during read transactions, usr_adr_inc will signal to the back-end that the pci core is ready to accept data. usr_adr_inc and usr_rdy both active during a read transaction signals a data transfer between the fpga and the pci core (and that the address counter must be incremented). usr_rddecode i this signal should be driven active when a user read command has been decoded from the usr_cbe[3:0] bus (while usr_adr_valid is active). this command may be mapped from any of the pci read commands, such as memory read, memory read line, memory read multiple, i/o read, etc. usr_wrdecode i this signal should be driven active when a user write command has been decoded from the usr_cbe[3:0] bus (while usr_adr_valid is active). this command may be mapped from any of the pci write commands, such as memory write or i/o write. internal interface signal descriptions
rev b 5 ql5130 - quickpci tm internal interface signal descriptions (continued) usr_select i this signal should be driven active when the address on usr_addr_wrdata[31:0] has been decoded and determined to be within the address space of the device. usr_addr_wrdata[31:0] must be compared to each of the valid base address registers in the pci configuration space. also, this signal must be gated by the memory access enable or i/o access enable registers in the pci configuration space (command register bits 1 or 0 at offset 04h). usr_write o this signal will be active throughout a user write transaction, which has been decoded by usr_wrdecode at the beginning of the transaction. the write-enable for individual double-words of data (on usr_addr_wrdata[31:0]) during a user write transaction should be generated by logically anding this signal with usr_adr_inc. cfg_write o this signal will be active throughout a configuration write transaction. the write-enable for individual double-words of data (on usr_addr_wrdata[31:0]) during a configuration write transaction should be generated by logically anding this signal with usr_adr_inc. cfg_rddata[31:0] i data from the pci configuration registers, required to be presented to the pci core during pci configuration reads. usr_rddata[31:0] i data from the back-end user logic, required to be presented during pci reads. cfg_cmdreg8 cfg_cmdreg6 i bits 6 and 8 from the command register in the pci configuration space (offset 04h). cfg_perr_det o parity error detected on the pci bus. when this signal is active, bit 15 of the status register must be set in the pci configuration space (offset 04h). cfg_serr_sig o system error asserted on the pci bus. when this signal is active, the signaled system error bit, bit 14 of the status register, must be set in the pci configuration space (offset 04h). usr_trdyn o copy of the trdyn signal as driven by the pci target interface. usr_stopn o copy of the stopn signal as driven by the pci target interface. usr_devsel o inverted copy of the devseln signal as driven by the pci target interface. usr_last_cycle_d1 o indicates that the last transfer in a pci transaction is occurring. rdpipe_stat[1:0] o indicates the number of dwords currently in the read pipeline (00 = 0 elements, 01 = 1 element, 11 = 2 elements). this value is important at the end of a transaction (i.e. when usr_last_cycle_d1 is active) if non-prefetchable memory is being read. non-prefetchable memory is defined as registers or memory elements whose value changes when they are read. examples are status registers which are cleared when they are read, or fifo memories, since consecutive reads from the same address in these elements may not produce the same data values. usr_rdy i used to delay (add wait states to) a pci transaction when the back end needs additional time. subject to pci latency restrictions. usr_stop i used to prematurely stop a pci target access on the next pci clock.
6 rev b ql5130 - quickpci tm array of logic cells a wide range of additional features complements the ql5130 device. the fpga portion of the device is 5 volt and 3.3-volt pci-compliant and can perform high-speed logic functions such as 160 mhz fifos. i/o pins provide individually controlled output enables, dedicated input/feedback registers, and full jtag capability for boundary scan and test. in addi- tion, the ql5130 device provides the benefits of non-volatility, high design security, immediate func- tionality on power-up, and a single chip solution. the ql5130 programmable logic architecture con- sists of an array of user-configurable logic building blocks, called logic cells, set beneath a grid of metal wiring channels similar to those of a gate array. through vialink ? elements located at the wire inter- sections, the output(s) of any cell may be pro- grammed to connect to the input(s) of any other cell. using the programmable logic in the ql5130, designers can quickly and easily customize their back-end design for any number of applications. figure 4. logic cell ram module features the ql5130 device has twelve 1,152-bit ram mod- ules, for a total of 13,824 ram bits. using two mode pins, designers can configure each module into 64 (deep) x18 (wide), 128x9, 256x4, or 512x2 blocks. see the figure below. the blocks are also easily cascadable to increase their effective width or depth. figure 5. ram module a rray of l ogic c ells qs a1 a2 a3 a4 a5 a6 os op b1 b2 c1 c2 ms d1 e1 np e2 d2 ns f1 f3 f5 f6 f2 f4 qc qr mp az oz qz nz fz mode: address buses [a:0] data buses [w:0] 64x18 [5:0] [17:0] 128x9 [6:0] [8:0] 256x4 [7:0] [3:0] 512x2 [8:0] [1:0] ram m odule f eatures mode[1:0] wa[a:0] wd[w:0] we wclk ram module asyncrd ra[a:0] rd[w:0] re rclk
rev b 7 ql5130 - quickpci tm the ram modules are dual-ported, with completely independent read and write ports and separate read and write clocks. the read ports support asynchronous and synchronous operation, while the write ports support synchronous opera- tion. each port has 18 data lines and 9 address lines, allowing word lengths of up to 18 bits and address spaces of up to 512 words. depending on the mode selected, however, some higher order data or address lines may not be used. the write enable (we) line acts as a clock enable for synchronous write operation. the read enable (re) acts as a clock enable for synchronous read opera- tion (asyncrd input low), or as a flow-through enable for asynchronous read operation (asyncrd input high). designers can cascade multiple ram modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. this approach allows up to 512-deep configurations as large as 28 bits wide in the ql5130 device. a similar technique can be used to create depths greater than 512 words. in this case, address signals higher than the eighth bit are encoded onto the write enable (we) input for write operations. the read data outputs are multiplexed together using encoded higher read address bits for the multiplexer select signals. jtag support jtag pins support ieee standard 1149.1a to provide boundary scan capability for the ql5130 device. six pins are dedicated to jtag and programming func- tions on each ql5130 device, and are unavailable for general design input and output signals. tdi, tdo, tck, tms, and trstb are jtag pins. a sixth pin, stm, is used only for programming. development tools software support for the ql5130 device is available through the quick works development package. this turnkey pc-based quick works package, shown in fig- ure 6, provides a complete esp software solution with design entry, logic synthesis, place and route, and sim- ulation. quick works includes vhdl, verilog, sche- matic, and mixed-mode entry with fast and efficient logic synthesis provided by the integrated synplicity synplify lite tool, specially tuned to take advantage of the ql5130 architecture. quick works also provides functional and timing simulation for guaranteed timing and source-level debugging. the unix-based quick tools and pc-based quick- works-lite packages are a subset of quick works and provide a solution for designers who use schematic- only design flow third-party tools for design entry, syn- thesis, or simulation. quick tools and quick works- lite read edif netlists and provide support for all quicklogic devices. quick tools and quick works-lite also support a wide range of third-party modeling and simulation tools. in addition, the pc-based package combines all the features of quick works-lite with the scs schematic capture environment, providing a low- cost design entry and compilation solution. figure 6. quickworks tool suite jtag s upport d evelopment t ools schematic schematic turbo hdl editor third party design entry & synthesis third party simulation vhdl/ vhdl/ verilog verilog scs tools silos iii simulator spde mixed-mode design mixed-mode design synplify- hdl synthesi quick works design software veribest
8 rev b ql5130 - quickpci tm ql5130 external device pins the ql5130 device pins are indicated in the table below. these are pins on the device, some of which connect to the pci bus, and others that are programmable as user io. * see quicknote 65 on the quicklogic web site for information on ram initialization. ql5130 e xternal d evice p ins type description in input. a standard input-only signal out totem pole output. a standard active output driver t/s tri-state. a bi-directional, tri- state input/output pin s/t/s sustained tri-state. an active low tri-state signal driven by one pci agent at a time. it must be driven high for at least one clock before being dis- abled (set to hi-z). a pull-up needs to be provided by the pci system central resource to sustain the inactive state once the active driver has released the signal. o/d open drain. allows multiple devices to share this pin as a wired-or. pin/bus name type function vcc in supply pin. tie to 3.3v supply. vccio in supply pin for i/o. set to 3.3v for 3.3v i/o, 5v for 5.0v compliant i/o gnd in ground pin. tie to gnd on the pcb. i/o t/s programmable input/output/tri- state/bi-directional pin. glck/i in programmable global network or input-only pin. tie to vcc or gnd if unused. aclk/i in programmable array network or input- only pin. tie to vcc or gnd if unused. tdi/ rsi* in jtag data in/ram init. serial data in. tie to vcc if unused. connect to serial eprom data for ram init. tdo/ rco* out jtag data out/ram init clock. leave unconnected if unused. connect to serial eprom clock for ram init. tck in jtag clock. tie to gnd if unused. tms in jtag test mode select. tie to vcc if unused. trstb/ rro* in jtag reset/ram init. reset out. tie to gnd if unused. connect to serial eprom reset for ram init. stm in quicklogic reserved pin. tie to gnd on the pcb.
rev b 9 ql5130 - quickpci tm external device pins e xternal d evice p ins pin/bus name type function ad[31:0] t/s pci address and data: 32 bit multiplexed address/data bus. cben[3:0] t/s pci bus command and byte enables: multiplexed bus which contains byte enables for ad[31:0] or the bus command during the address phase of a pci transac- tion. par t/s pci parity: even parity across ad[31:0] and c/ ben[3:0] busses. driven one clock after address or data phases. master drives par on address cycles and pci writes. the target drives par on pci reads. framen s/t/s pci cycle frame: driven active by current pci master during a pci transaction. driven low to indicate the address cycle, driven high at the end of the transaction. devseln s/t/s pci device select. driven by a target that has decoded a valid base address. clk in pci system clock input. rstn in pci system reset input perrn s/t/s pci data parity error. driven active by the initiator or target two clock cycles after a data parity error is detected on the ad and c/ben busses. serrn o/d pci system error: driven active when an address cycle parity error, data parity error during a special cycle, or other catastrophic error is detected. idsel in pci initialization device select. use to select a specific pci agent during system initialization. irdyn s/t/s pci initiator ready. indicates the initiators ability to complete a read or write transaction. data transfer occurs only on clock cycles where both irdyn and trdyn are active. trdyn s/t/s pci target ready. indicates the targets ability to com- plete a read or write transaction. data transfer occurs only on clock cycles where both irdyn and trdyn are active. stopn s/t/s pci stop. used by a pci target to end a burst transac- tion.
10 rev b ql5130 - quickpci tm figure 7. 144-pin tqfp figure 8. 208-pin pqfp figure 9. 256-pin pbga ql5130-33apf144c quickpci pin #73 pin #1 pin #37 pin #109 QL5130-33APQ208C quickpci pin #1 pin # 53 pin # 105 pin #157 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c e d f g h k j l m n r p t u v y w bottom view pin a1 corner
rev b 11 ql5130 - quickpci tm ql5130 - 144 tqfp pinout pf144 function pf144 function pf144 function pf144 function 1 i/o 37 ad[21] 73 ad[4] 109 tck 2i/o38 tdi/rsi 74 ad[3] 110 stm 3 i/o 39 ad[20] 75 ad[2] 111 i/o 4 i/o 40 ad[19] 76 ad[1] 112 i/o 5 i/o 41 ad[18] 77 ad[0] 113 i/o 6i/o42 vcc 78 i/o 114 vcc 7 vcc 43 ad[17] 79 vcc 115 i/o 8 i/o 44 ad[16] 80 i/o 116 i/o 9 i/o 45 cben[2] 81 i/o 117 i/o 10 i/o 46 framen 82 i/o 118 i/o 11 i/o 47 irdyn 83 i/o 119 i/o 12 i/o 48 trdyn 84 i/o 120 i/o 13 i/o 49 devseln 85 i/o 121 i/o 14 i/o 50 gnd 86 i/o 122 gnd 15 gnd 51 stopn 87 gnd 123 i/o 16 i/o 52 perrn 88 i/o 124 i/o 17 gclk/i 53 serrn 89 gclk/i 125 i/o 18 aclk/i 54 gnd 90 aclk/i 126 gnd 19 vcc 55 par 91 vcc 127 i/o 20 rstn 56 cben[1] 92 gclk/i 128 i/o 21 clk 57 ad[15] 93 gclk/i 129 i/o 22 vcc 58 vccio 94 vcc 130 vccio 23 i/o 59 ad[14] 95 i/o 131 i/o 24 ad[31] 60 ad[13] 96 i/o 132 i/o 25 ad[30] 61 ad[12] 97 i/o 133 i/o 26 ad[29] 62 ad[11] 98 i/o 134 i/o 27 ad[28] 63 ad[10] 99 i/o 135 i/o 28 ad[27] 64 ad[9] 100 i/o 136 i/o 29 ad[26] 65 ad[8] 101 i/o 137 i/o 30 gnd 66 gnd 102 gnd 138 gnd 31 ad[25] 67 cben[0] 103 i/o 139 i/o 32 ad[24] 68 ad[7] 104 i/o 140 i/o 33 cben[3] 69 ad[6] 105 i/o 141 i/o 34 idsel 70 ad[5] 106 i/o 142 i/o 35 ad[23] 71 trstb/rro 107 i/o 143 tdo/rco 36 ad[22] 72 tms 108 i/o 144 i/o ql5130 - 144 tqfp p inout
12 rev b ql5130 - quickpci tm ql5130 - 208 pqfp pinout ql5130 - 208 pqfp p inout p q 208 function p q 20 function p q 208 function p q 208 function p q 208 function 1 i/o 43 gnd 85 ad[3] 127 gnd 169 i/o 2 i/o 44 idsel 86 ad[2] 128 i/o 170 i/o 3 i/o 45 ad[23] 87 ad[1] 129 gclk/i 171 i/o 4 i/o 46 ad[22] 88 ad[0] 130 aclk/i 172 i/o 5 i/o 47 ad[21] 89 i/o 131 vcc 173 i/o 6 i/o 48 ad[20] 90 i/o 132 gclk/i 174 i/o 7 i/o 49 ad[19] 91 i/o 133 gclk/i 175 i/o 8 i/o 50 ad[18] 92 i/o 134 vcc 176 i/o 9 i/o 51 ad[17] 93 i/o 135 i/o 177 gnd 10 vcc 52 ad[16] 94 i/o 136 i/o 178 i/o 11 i/o 53 cben[2] 95 gnd 137 i/o 179 i/o 12 gnd 54 tdi 96 i/o 138 i/o 180 i/o 13 i/o 55 framen 97 vcc 139 i/o 181 i/o 14 i/o 56 irdyn 98 i/o 140 i/o 182 gnd 15 i/o 57 trdyn 99 i/o 141 i/o 183 i/o 16 i/o 58 devseln 100 i/o 142 i/o 184 i/o 17 i/o 59 gnd 101 i/o 143 i/o 185 i/o 18 i/o 60 stopn 102 i/o 144 i/o 186 i/o 19 i/o 61 vcc 103 trstb 145 vcc 187 vccio 20 i/o 62 i/o 104 tms 146 i/o 188 i/o 21 i/o 63 i/o 105 i/o 147 gnd 189 i/o 22 i/o 64 perrn 106 i/o 148 i/o 190 i/o 23 gnd 65 i/o 107 i/o 149 i/o 191 i/o 24 i/o 66 serrn 108 i/o 150 i/o 192 i/o 25 rstn 67 par 109 i/o 151 i/o 193 i/o 26 aclk/i 68 cben[1] 110 i/o 152 i/o 194 i/o 27 vcc 69 ad[15] 111 i/o 153 i/o 195 i/o 28 gclk/i 70 ad[14] 112 i/o 154 i/o 196 i/o 29 clk 71 ad[13] 113 i/o 155 i/o 197 i/o 30 vcc 72 ad[12] 114 vcc 156 i/o 198 i/o 31 i/o 73 gnd 115 i/o 157 tck 199 gnd 32 i/o 74 ad[11] 116 gnd 158 stm 200 i/o 33 ad[31] 75 ad[10] 117 i/o 159 i/o 201 vcc 34 ad[30] 76 ad[9] 118 i/o 160 i/o 202 i/o 35 ad[29] 77 ad[8] 119 i/o 161 i/o 203 i/o 36 ad[28] 78 gnd 120 i/o 162 i/o 204 i/o 37 ad[27] 79 cben[0] 121 i/o 163 gnd 205 i/o 38 ad[26] 80 ad[7] 122 i/o 164 i/o 206 i/o 39 ad[25] 81 ad[6] 123 i/o 165 vcc 207 tdo 40 ad[24] 82 ad[5] 124 i/o 166 i/o 208 i/o 41 vcc 83 vccio 125 i/o 167 i/o 42 cben[3] 84 ad[4] 126 i/o 168 i/o
rev b 13 ql5130 - quickpci tm ql5130 - 256 pbga pinout ql5130 - 256 pbga p inout pb256 function pb256 function pb256 function pb256 function pb256 function pb256 function a1 gnd c4 i/o e19 i/o l2 aclk/i t17 i/o v20 i/o a2 i/o c5 i/o e20 i/o l3 rstn t18 i/o w1 i/o a3 i/o c6 i/o f1 i/o l4 gclk/i t19 nc w2 i/o a4 i/o c7 i/o f2 i/o l17 vcc t20 i/o w3 tdi a5 i/o c8 i/o f3 i/o l18 i/o u1 i/o w4 i/o a6 i/o c9 vccio f4 vcc l19 i/o u2 i/o w5 ad[27] a7 i/o c10 i/o f17 vcc l20 i/o u3 i/o w6 cben[3] a8 i/o c11 i/o f18 nc m1 i/o u4 gnd w7 ad[21] a9 i/o c12 i/o f19 i/o m2 i/o u5 ad[26] w8 ad[20] a10 i/o c13 i/o f20 i/o m3 i/o u6 vcc w9 cben[2] a11 i/o c14 i/o g1 i/o m4 nc u7 ad[22] w10 devseln a12 i/o c15 i/o g2 nc m17 nc u8 gnd w11 perrn a13 i/o c16 i/o g3 i/o m18 i/o u9 framen w12 cben[1] a14 i/o c17 i/o g4 i/o m19 i/o u10 vcc w13 par a15 i/o c18 i/o g17 i/o m20 i/o u11 i/o w14 ad[10] a16 i/o c19 i/o g18 i/o n1 i/o u12 i/o w15 ad[9] a17 i/o c20 i/o g19 nc n2 i/o u13 gnd w16 ad[5] a18 i/o d1 i/o g20 i/o n3 i/o u14 ad[11] w17 ad[1] a19 tck d2 i/o h1 i/o n4 gnd u15 vcc w18 ad[0] a20 i/o d3 i/o h2 i/o n17 gnd u16 ad[4] w19 i/o b1 tdod4gndh3 i/on18i/ou17gndw20trstb b2 i/o d5 i/o h4 gnd n19 i/o u18 i/o y1 i/o b3 i/o d6vcch17gndn20i/ou19i/o y2 nc b4 i/o d7 i/o h18 i/o p1 i/o u20 i/o y3 i/o b5 i/o d8 gnd h19 i/o p2 i/o v1 i/o y4 ad[31] b6 i/o d9 i/o h20 i/o p3 i/o v2 nc y5 ad[29] b7 i/o d10 i/o j1 i/o p4 i/o v3 i/o y6 ad[25] b8 i/o d11 vcc j2 i/o p17 i/o v4 ad[30] y7 ad[23] b9 i/o d12 i/o j3 nc p18 i/o v5 ad[28] y8 ad[19] b10 i/o d13 gnd j4 i/o p19 nc v6 ad[24] y9 ad[17] b11 i/o d14 i/o j17 nc p20 i/o v7 idsel y10 irdyn b12 i/o d15 vcc j18 i/o r1 nc v8 ad[18] y11 i/o b13 i/o d16 i/o j19 i/o r2 i/o v9 ad[16] y12 serrn b14 i/o d17 gnd j20 gclk / i r3 i/o v10 trdyn y13 ad[14] b15 i/o d18 i/o k1 i/o r4 vcc v11 stopn y14 ad[12] b16 i/o d19 i/o k2 i/o r17 vcc v12 vccio y15 ad[8] b17 nc d20 i/o k3 i/o r18 i/o v13 ad[15] y16 ad[7] b18 stm e1 nc k4 vcc r19 i/o v14 ad[13] y17 ad[3] b19 nc e2 i/o k17 gclk/i r20 i/o v15 cben[0] y18 i/o b20 i/o e3 i/o k18 aclk/i t1 nc v16 ad[6] y19 i/o c1 i/o e4 i/o k19 gclk/i t2 i/o v17 ad[2] y20 nc c2 i/o e17 i/o k20 nc t3 i/o v18 i/o c3 i/o e18 i/o l1 clk t4 nc v19 tms
14 rev b ql5130 - quickpci tm absolute maximum ratings operating range dc characteristics dc input current ........................... ..... 20 ma esd pad protection ....................... ..... 2000v storage temperature .............. -65 c to +150c lead temperature .............................. ...300 c vcc voltage ............ ............-0.5 to 4.6v vccio voltage......... ............-0.5 to 7.0v input voltage ............-0.5 to vccio+0.5v latch-up immunity ................. ..... 200 ma symbol parameter industrial commercial unit min max min max vcc supply voltage 3.0 3.6 3.0 3.6 v vccio i/o input tolerance voltage 3.0 5.5 3.0 5.25 v ta ambient temperature -40 85 0 70 c k delay factor -a speed grade 0.43 0.90 0.46 0.88 symbol parameter conditions min max unit vih input high voltage 0.5vcc vccio+0.5 v vil input low voltage -0.5 0.3vcc v voh output high voltage ioh = -12 ma 2.4 v ioh = -500 m a 0.9vcc v vol output low voltage iol = 16 ma 0.45 v iol = 1.5 ma 0.1vcc v ii i or i/o input leakage current vi = vccio or gnd -10 10 m a ioz 3-state output leaka g e current vi = vccio or gnd -10 10 m a ci input capacitance [1] 10 pf ios output short circuit current [2] vo = gnd -15 -180 ma vo = vcc 40 210 ma icc d.c. supply current [3] vi , vio = vccio or gnd 0.50 ( t y p ) 2ma iccio d.c. supply current on vccio 0 100 m a [1] capacitance is sample tested only. clock pins are 12 pf maximum. [2] only one output at a time. duration should not exceed 30 seconds. [3] for -a commercial grade device only. maximum icc is 3 ma for all industrial grade devices. for ac conditions, contact quicklogic customer engineering.
rev b 15 ql5130 - quickpci tm ac characteristics at vcc = 3.3v, ta = 25 c (k = 1.00) (to calculate delays, multiply the appropriate k factor in the operating range section by the following numbers.) logic cells ram cell synchronous write timing notes: [4] stated timing for worst case propagation delay over process variation at vcc=3.3v and ta=25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. [5] these limits are derived from a representative selection of the slowest paths through the quickram logic cell including typical net delays. worst case delay values for specific paths should be determined from timing analy- sis of your particular design. symbol parameter propagation delays (ns) fanout [5] 12348 tpd combinatorial delay [6] 1.4 1.7 1.9 2.2 3.2 tsu setup time [6] 1.7 1.7 1.7 1.7 1.7 th hold time 0.0 0.0 0.0 0.0 0.0 tclk clock to q delay 0.7 1.0 1.2 1.5 2.5 tcwhi clock high time 1.2 1.2 1.2 1.2 1.2 tcwlo clock low time 1.2 1.2 1.2 1.2 1.2 tset set delay 1.0 1.3 1.5 1.8 2.8 treset reset delay 0.8 1.1 1.3 1.6 2.6 tsw set width 1.9 1.9 1.9 1.9 1.9 trw reset width 1.8 1.8 1.8 1.8 1.8 symbol parameter propagation delays (ns) fanout 12348 tswa wa setup time to wclk 1.0 1.0 1.0 1.0 1.0 thwa wa hold time to wclk 0.0 0.0 0.0 0.0 0.0 tswd wd setup time to wclk 1.0 1.0 1.0 1.0 1.0 thwd wd hold time to wclk 0.0 0.0 0.0 0.0 0.0 tswe we setup time to wclk 1.0 1.0 1.0 1.0 1.0 thwe we hold time to wclk 0.0 0.0 0.0 0.0 0.0 twcrd wclk to rd (wa=ra) [4] 5.0 5.3 5.6 5.9 7.1
16 rev b ql5130 - quickpci tm ram cell synchronous read timing ram cell asynchronous read t iming input-only cells clock cells notes: [6] the array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. the number of half columns used does not affect clock buffer delay. the array clock has up to 8 loads per half column. the global clock has up to 11 loads per half column. symbol parameter propagation delays (ns) fanout 12348 tsra ra setup time to rclk 1.0 1.0 1.0 1.0 1.0 thra ra hold time to rclk 0.0 0.0 0.0 0.0 0.0 tsre re setup time to rclk 1.0 1.0 1.0 1.0 1.0 thre re hold time to rclk 0.0 0.0 0.0 0.0 0.0 trcrd rclk to rd [4] 4.0 4.3 4.6 4.9 6.1 symbol parameter propagation delays (ns) fanout 12348 rpdrd ra to rd [ 4 ] 3.0 3.3 3.6 3.9 5.1 symbol parameter propagation delays (ns) fanout [5] 123481224 tin high drive input delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 tini high drive input, inverting delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 tlclk input register clock to q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 tlrst input register reset delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 tlesu input register clock enable setup time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 symbol parameter propagation delays (ns) loads per half column [7] 123481011 tack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 tgckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 tgckb global clock buffer delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3
rev b 17 ql5130 - quickpci tm i/o cell input delays i/o cell output delays notes: [7] the following loads are used for tpxz: symbol parameter propagation delays (ns) fanout [5] 1234810 ti/o input delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 tloclk input register clock to q 0.7 1.0 1.2 1.5 2.5 3.0 tlorst input register reset delay 0.6 0.9 1.1 1.4 2.4 2.9 tlesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 symbol parameter propagation delays (ns) output load capacitance (pf) 30 50 75 100 150 toutlh output delay low to high 2.1 2.5 3.1 3.6 4.7 touthl output delay high to low 2.2 2.6 3.2 3.7 4.8 tpzh output delay tri-state to high 1.2 1.7 2.2 2.8 3.9 tpzl output delay tri-state to low 1.6 2.0 2.6 3.1 4.2 tphz output delay high to tri-state [8] 2.0 tplz output delay low to tri-state [8] 1.2 5 pf 1k w 5 pf 1k w tphz tplz

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